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19-3488; Rev 1; 1/05
KIT ATION EVALU LE VAILAB A
Multichannel, True-Differential, Serial, 14-Bit ADCs
General Description Features
8-Channel Single-Ended or 4-Channel Differential Inputs (MAX1148/MAX1149) 4-Channel Single-Ended or 2-Channel Differential Inputs (MAX1146/MAX1147) Internal Multiplexer and T/H Single-Supply Operation 4.75V to 5.25V Supply (MAX1146/MAX1148) 2.7V to 3.6V Supply (MAX1147/MAX1149) Internal Reference +4.096V (MAX1146/MAX1148) +2.500V (MAX1147/MAX1149) 116ksps Sampling Rate Low Power 1.1mA (116ksps) 120A (10ksps) 12A (1ksps) 300nA (Power-Down Mode) SPI-/QSPI-/MICROWIRE Compatible 20-Pin TSSOP
MAX1146-MAX1149
The MAX1146-MAX1149 low-power, 14-bit, multichannel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H), voltage reference, and clock. The MAX1146/MAX1148 operate from a single +4.75V to +5.25V supply, and the MAX1147/MAX1149 operate from a single +2.7V to +3.6V supply. All analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPITM/QSPITM/MICROWIRETM devices without external logic. The serial strobe output (SSTRB) allows convenient connection to digital signal processors. The MAX1146-MAX1149 use an internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions. The MAX1146/MAX1148 include an internal +4.096V reference, while the MAX1147/MAX1149 include an internal +2.500V reference. All devices accept an external reference from 1.5V to VDD. The MAX1146-MAX1149 provide a hardware shutdown and two software power-down modes. Using the software power-down modes allows the devices to be powered down between conversions. When powered down, accessing the serial interface automatically powers up the devices. The quick turn-on time allows power-down between all conversions. This technique reduces supply current to under 120A for quick turn-on. The MAX1146-MAX1149 are available in a 20-pin TSSOP package.
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Process Control
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
PART MAX1146BCUP MAX1146BEUP MAX1147BCUP MAX1147BEUP MAX1148BCUP MAX1148BEUP MAX1149BCUP MAX1149BEUP TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C PINPACKAGE 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP 20 TSSOP INL (LSB) 2 2 2 2 2 2 2 2 INPUT CHANNELS 4 4 4 4 8 8 8 8 INTERNAL REFERENCE (V) +4.096 +4.096 +2.500 +2.500 +4.096 +4.096 +2.500 +2.500
________________________________________________________________ Maxim Integrated Products
1
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ............................................-0.3V to +6.0V AGND to DGND.....................................................-0.3V to +0.3V CH0-CH7, COM to AGND..........................-0.3V to (VDD + 0.3V) REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V) Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) 20 TSSOP (derate 10.9mW/C above +70C) .............879mW Operating Temperature Ranges MAX114_ BC_ _ ..................................................0C to +70C MAX114_ BE_ _ ...............................................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2F, external +4.096V reference at REF (MAX1146/ MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Offset Temperature Coefficient Gain Error Gain Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching (Note 3) 0.8 1 1 0.3 20 INL DNL No missing codes over temperature -1.0 14 0.7 0.5 2 +1.5 10 Bits LSB LSB LSB ppm/C LSB ppm/C LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (1kHz sine-wave input, 2.5VP-P, full-scale analog input, 116ksps, 2.1MHz external clock) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Conversion Time (Note 5) SSBW FPBW SINAD THD SFDR (Note 4) -3dB point SINAD > 68dB External clock, 2.1MHz 15 SCLK cycles Internal clock 7.2 6 8 Up to the 5th harmonic 84 77 81 -96 98 -85 3.0 2.0 -88 dB dB dB dB MHz MHz
tCONV
s
2
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Multichannel, True-Differential, Serial, 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2F, external +4.096V reference at REF (MAX1146/ MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS Internal clock mode, fSCLK = 2.1MHz 18 clocks/conversion 24 clocks/conversion MIN TYP MAX 60.3 51.5 116.66 87.50 1.4 20 <50 External clock mode Internal clock mode 0.1 0 2.1 Unipolar, COM = 0 Bipolar, COM = VREF / 2, single-ended On/off-leakage current, VCH_ = 0 to VDD 0.01 18 MAX1147/MAX1149, TA = +25C MAX1146/MAX1148, TA = +25C REF = DGND MAX114_ BC _ _ MAX114_ BE _ _ 0 to 0.2mA output load (Note 8) 2 0.01 1.250 18 Pull REFADJ high to disable the internal bandgap reference and reference buffer MAX1147/MAX1149 MAX1146/MAX1148 VDD 0.25V 2.000 3.277 30 40 2.0 2.480 4.076 2.500 4.096 2.520 4.116 20 50 60 0 VREF VREF / 2 1 2.1 2.1 s ns ps MHz MHz ksps UNITS
MAX1146-MAX1149
Throughput Rate
fSAMPLE
External clock mode, 18 clocks/conversion fSCLK = 2.1MHz 24 clocks/conversion
T/H Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Internal Clock Frequency ANALOG INPUTS (CH0-CH7, COM) Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance
tACQ tAD tAJ fSCLK
V A pF
INTERNAL REFERENCE (CREF = 2.2F, CREFADJ = 0.01F) REF Output Voltage REF Short-Circuit Current VREF Tempco (Note 7) Load Regulation Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Logic High Reference Buffer Voltage Gain VREF IREFSC V mA ppm/C mV F F V mV V V/V
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2F, external +4.096V reference at REF (MAX1146/ MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER EXTERNAL REFERENCE AT REF REF Input Voltage Range REF Input Current REF Input Resistance DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUT (DOUT, SSTRB) Output-Voltage Low Output-Voltage High Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage VDD MAX1147/MAX1149 MAX1146/MAX1148 Normal operation, fullscale input Fast power-down Shutdown Supply Current (Note 8) Power-Supply Rejection (Note 9) PSR Full power-down SHDN = DGND External reference External reference 116ksps 10ksps 1ksps 2.7 4.75 1.1 0.12 0.012 1.9 120 0.3 0.3 0.2 10 mV A 3.6 5.25 1.5 mA V VOL VOH IL COUT ISINK = 2mA ISOURCE = 2mA CS = VDD CS = VDD 10 VDD - 0.5 10 0.4 V V A pF VIH VIL VHYST IIN CIN 10 0.2 1 VDD < 3.6V VDD > 3.6V 2.0 3.0 0.8 V V V A pF VREF IREF 1.5 125 Shutdown 6 0.01 8 VDD + 50mV 450 10 V A k SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current (Note 8)
IDD
Internal reference at 116ksps
2.4
mA
4
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Multichannel, True-Differential, Serial, 14-Bit ADCs
TIMING CHARACTERISTICS
(VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2F, external +4.096V reference at REF for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figures 1, 2, and 3)
PARAMETER DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Fall to Output Data Valid CS Fall to DOUT Enable CS Rise to DOUT Disable SHDN Rise CS Fall to SCLK Rise Time SHDN Rise CS Fall to SCLK Rise Hold Time SCLK Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SSTRB Output Enable CS Rise to SSTRB Output Disable SSTRB Rise to SCLK Rise SCLK Fall to SSTRB Edge CS Pulse Width SYMBOL tDS tDH tDOV tDOE tDOD tCSS tCSH fSCLK tCH tCL tSTE tSTD tSCK tSCST tCSW 100 External clock mode Internal clock mode Internal clock mode Internal clock mode External clock mode only External clock mode only Internal clock mode only 0 80 CLOAD = 50pF CLOAD = 50pF CLOAD = 50pF 50 50 0.1 0 100 100 120 120 2.1 2.1 CONDITIONS MIN 50 0 10 80 120 120 TYP MAX UNITS ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns
MAX1146-MAX1149
Note 1: Tested at VDD = 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM = 0; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Measured with external reference. Note 4: "On" channel grounded; full-scale 1kHz sine wave applied to all "off" channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See Figures 8-11.) Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: Digital inputs equal VDD or DGND. Note 8: External load should not change during conversion for specified accuracy. Note 9: Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the MAX1146/MAX1148. VDD = 3.6V to 2.7V for MAX1147/MAX1149 and VDD = 5.25V to 4.75V for the MAX1146/MAX1148.
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
VDD VDD 6k DOUT CLOAD 50pF DGND DOUT CLOAD 50pF DGND b) HIGH-Z TO VOL AND VOH TO VOL DOUT CLOAD 50pF DGND DOUT CLOAD 50pF DGND b) VOL TO HIGH-Z
6k
6k
6k
DGND
DGND a) VOH TO HIGH-Z
a) HIGH-Z TO VOH AND VOL TO VOH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
CS tCSS tCSH SCLK 1 tCL 1 fSCLK tDS DIN
START SEL2 SEL1 SEL0 SGL/DIF UNI/BIP
tCH
tCSW
8 tSCK tDH
PD1 PD0
9
24
tDOE DOUT HIGH-Z tSTE SSTRB (EXTERNAL CLOCK MODE) HIGH-Z
tACQ tDOV D13 tSCST D12 D11 D10 D2 D1 D0
tDOD HIGH-Z
tSTD HIGH-Z
tSCST SSTRB (INTERNAL CLOCK MODE)
Figure 3. Detailed Operating Characteristics
6
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Multichannel, True-Differential, Serial, 14-Bit ADCs
Typical Operating Characteristics
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2F, CLOAD = 50pF, TA = +25C, unless otherwise noted.)
INL vs. OUTPUT CODE
MAX1146 toc01
MAX1146-MAX1149
DNL vs. OUTPUT CODE
MAX1146 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 EXTERNAL REFERENCE
MAX1146 toc03
1.5 1.0 0.5 INL (LSB)
1.5 1.0 0.5 DNL (LSB) 0 -0.5 -1.0 -1.5
2.0 INTERNAL REFERENCE
0 -0.5 -1.0 -1.5 0 4096 8192 OUTPUT CODE 12288 16384
0 0 4096 8192 OUTPUT CODE 12288 16384 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc04
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc05
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
SHUTDOWN SUPPLY CURRENT (A) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
MAX1146 toc06
2.0 1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 EXTERNAL REFERENCE INTERNAL REFERENCE
1.8 SHUTDOWN SUPPLY CURRENT (A) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
0.45
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 SUPPLY VOLTAGE (V)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. CONVERSION RATE
MAX1146 toc07
SUPPLY CURRENT vs. TEMPERATURE
MAX1146 toc08
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 MAX1147/MAX1149 MAX1146/MAX1148
MAX1146 toc09
1200 1000 SUPPLY CURRENT (A) 800 600 400 200 0 0.01 0.1 1 10
2.5 MAX1146/MAX1148 INTERNAL REFERENCE MAX1147/MAX1149 INTERNAL REFERENCE 1.5 MAX1146/MAX1148 EXTERNAL REFERENCE 1.0 MAX1147/MAX1149 EXTERNAL REFERENCE
4.5
2.0 SUPPLY CURRENT (mA)
FAST POWER-DOWN
0.5 FULL POWER-DOWN 0 100 1000 -40 -15 10 35 60 85 CONVERSION RATE (ksps) TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2F, CLOAD = 50pF, TA = +25C, unless otherwise noted.)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc10
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc11
REFERENCE VOLTAGE vs. TEMPERATURE (MAX1146/MAX1148)
4.099 REFERENCE VOLTAGE (V) 4.098 4.097 4.096 4.095 4.094 4.093 4.092
MAX1146 toc12
4.0980 4.0975 REFERENCE VOLTAGE (V) 4.0970 4.0965 4.0960 4.0955 4.0950 4.0945 4.0940 4.75 4.85 4.95 5.05 5.15
2.5020 2.5015 REFERENCE VOLTAGE (V) 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 2.4980
4.100
4.091 4.090 2.7 3.0 3.3 3.6 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
5.25
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE vs. TEMPERATURE (MAX1147/MAX1149)
MAX1146 toc13
REFERENCE BUFFER POWER-UP DELAY vs. TIME IN SHUTDOWN
CREF = 4.7F CREFADJ = 0.01F 2000 DELAY (s)
MAX1146 toc14
2.503 2.502 REFERENCE VOLTAGE (V) 2.501 2.500 2.499 2.498 2.497 -40 -15 10 35 60
2500
1500
1000
500
85
0 0.001
0.01
0.1
1
10
TEMPERATURE (C)
TIME IN SHUTDOWN (s)
FFT PLOT
20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 1000 2000 3000
MAX1146 toc15
EFFECTIVE NUMBER OF BITS vs. FREQUENCY
12.9 EFFECTIVE NUMBER OF BITS 12.8 12.7 12.6 12.5 12.4 12.3 12.2 12.1 12.0
MAX1146 toc16
13.0
fIN = 1kHz fSAMPLE = 116ksps VDD = 5V/3V
AMPLITUDE (dB)
4000
5000
1
10
19
28
37
46
55
FREQUENCY (Hz)
FREQUENCY (kHz)
8
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Multichannel, True-Differential, Serial, 14-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2F, CLOAD = 50pF, TA = +25C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc17
MAX1146-MAX1149
OFFSET ERROR vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
-1 OFFSET ERROR (LSB) -2 -3 -4 -5 -6
MAX1146 toc18
6 4 OFFSET ERROR (LSB) 2 0 -2 -4 -6 2.7 3.0 3.3
0
-7 -8 3.6 4.75 4.85 4.95 5.05 5.15 5.25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
GAIN ERROR vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc19
GAIN ERROR vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc20
6 4 GAIN ERROR (LSB) 2 0 -2 -4 -6 2.7 3.0 3.3
6 4 GAIN ERROR (LSB) 2 0 -2 -4 -6
3.6
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CHANNEL-TO-CHANNEL GAIN MATCHING vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc21
CHANNEL-TO-CHANNEL GAIN MATCHING vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
XMAX1146 toc22
6 4 GAIN MATCHING (LSB) 2 0 -2 -4 -6 2.7 3.0 3.3
6 4 GAIN MATCHING (LSB) 2 0 -2 -4 -6
3.6
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), external +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2F, CLOAD = 50pF, TA = +25C, unless otherwise noted.)
CHANNEL-TO-CHANNEL GAIN MATCHING vs. TEMPERATURE
MAX1146 toc23
CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc24
6 4 GAIN MATCHING (LSB) 2 0 -2 -4 -6 -40 -15 10 35 60
6 4 OFFSET MATCHING (LSB) 2 0 -2 -4 -6
85
2.7
3.0
3.3
3.6
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc25
CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE
MAX1146 toc26
6 4 OFFSET MATCHING (LSB) 2 0 -2 -4 -6 4.75 4.85 4.95 5.05 5.15
6 4 OFFSET MATCHING (LSB) 2 0 -2 -4 -6
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX1146 toc27
OFFSET ERROR vs. TEMPERATURE
MAX1146 toc28
6 4 GAIN ERROR (LSB) 2 0 -2 -4 -6 -40 -15 10 35 60
6 4 OFFSET ERROR (LSB) 2 0 -2 -4 -6
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
10
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Multichannel, True-Differential, Serial, 14-Bit ADCs
Pin Description
PIN MAX1148 MAX1146 MAX1149 MAX1147 1 2 3 4 5 6 7 8 9 10 1 2 3 4 -- -- -- -- 9 10 NAME CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM SHDN Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in unipolar and bipolar mode. Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current to 0.2A. Driving shutdown high enables the devices. Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the MAX1147/MAX1149 VREF is +2.500V. Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01F capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and referencebuffer amplifier. Analog Ground Digital Ground Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is high impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high (external clock mode). Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high impedance when CS is high. Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed in external clock mode. (Duty cycle must be 40% to 60%.) Positive Supply Voltage. Bypass to AGND with a 0.1F capacitor. No Connection. Not internally connected. Analog Inputs FUNCTION
MAX1146-MAX1149
11
11
REF
12 13 14 15
12 13 14 15
REFADJ AGND DGND DOUT
16
16
SSTRB
17 18 19 20 --
17 18 19 20 5-8
DIN CS SCLK VDD N.C.
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11
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Detailed Description
The MAX1146-MAX1149 ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 14-bit digital output. A flexible serial interface provides easy interface to microprocessors (Ps). Figure 4 shows the typical application circuit and Figure 5 shows a functional diagram of the MAX1148/MAX1149. In single-ended mode, the analog input MUX connects IN+ to the selected input channel and IN- to COM. In differential mode, IN+ and IN- are connected to the selected analog input pairs such as CH0/CH1. Select the analog input channels according to Tables 1-5. The analog input multiplexer switches to the selected channel on the control byte's fifth SCLK falling edge. At this time, the T/H switches are in the track position and CT/H+ and CT/H- track the analog input signal. At the control byte's eighth SCLK falling edge, the MUX opens and the T/H switches move to the hold position, retaining the charge on CT/H+ and CT/H- as a sample of the input signal. See Figures 8-11 for input MUX and T/H switch positioning. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator-input voltage to 0 within the limits of 14-bit resolution. This action requires 15 conversion clock cycles and is equivalent to transferring a charge of 18pF x (VIN+ - VIN-) from C T/H+ and C T/H- to the binary-weighted capacitive DAC, forming a digital representation of the analog input signal. After conversion, the T/H switches move from the hold position to the track position and the MUX switches back to the last specified position. In internal clock mode, the conversion is complete on the rising edge of SSTRB. In external clock mode, the conversion is complete on the eighteenth SCLK falling edge. The time required for the T/H to acquire an input signal is a function of the analog input source impedance. If the input signal source impedance is high, the acquisition time lengthens. The MAX1146-MAX1149 provide three SCLK cycles (tACQ) in which the T/H capacitance must acquire a charge representing the input signal, typically the last three SCLKs of the control word. The input source impedance (RSOURCE) should be minimized to allow the T/H capacitance to charge within this allotted time. tACQ = 11.5 x (RSOURCE + RIN) x CIN where RSOURCE is the analog input source impedance, RIN is 2.6k (which is the sum of the analog input MUX and T/H switch resistances), and CIN is 18pF (which is the sum of CT/H+, CT/H-, and input stray capacitance). To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to AGND. This input capacitor reduces the input's AC impedance but forms an RC filter with the source impedance, limiting the analog input bandwidth. For larger source impedance, use a buffer amplifier such as the MAX4430 to maintain analog input signal integrity.
True-Differential Analog Input and Track/Hold
The MAX1146-MAX1149 analog input architecture contains an analog input multiplexer (MUX), two T/H capacitors, T/H switches, a comparator, and two switched capacitor digital-to-analog converters (DACs) (Figure 6).
VDD 10 CH0 CH1 CH2 ANALOG INPUTS CH3 CH4 CH5 CH6 CH7 REF 2.2F COM AGND VDD 0.1F 4.7F VDD
MAX1148 MAX1149
SHDN SCLK CS DIN SSTRB DOUT
I/O SCK I/O MOSI I/O MISO 0.01F VSS P
REFADJ DGND
Figure 4. Typical Application Circuit
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM +1.250V BANDGAP REFERENCE REFADJ REF 20k INPUT SHIFT REGISTER INTERNAL CLOCK
CONTROL LOGIC
ANALOG INPUT MUX
OUTPUT SHIFT REGISTER T/H IN CLOCK SAR OUT ADC REF
DOUT SSTRB
VDD
MAX1149
AV = 2.0V/V
DGND AGND
Figure 5. Functional Diagram 12 ______________________________________________________________________________________
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
ANALOG INPUT MUX
CH0
MAX1148 MAX1149
REF
CH1
CH2 IN+ CH3
CT/H+ 14-BIT CAPACITIVE DAC TRACK
CH4
HOLD HOLD
CH5
HOLD TRACK
TRACK 14-BIT CAPACITIVE DAC
CH6
INCT/H-
CH7 REF
COM
Figure 6. Equivalent Input Circuit
Input Bandwidth
The MAX1146-MAX1149 feature input tracking circuitry with a 3.0MHz small-signal bandwidth. The 3.0MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Quick Look
Use the circuit of Figure 7 to quickly evaluate the MAX1148/MAX1149. The MAX1148/MAX1149 require a control byte to be written to DIN using SCLK before each conversion. Connecting DIN to VDD and clocking SCLK feeds in a control byte of $FF HEX (see Table 1). Trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for two clock periods before the MSB of the 14-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 alters the sequence of bits from DOUT. A total of 18 clock cycles are required per conversion (Figure 10). All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK.
Analog Input Protection
Internal protection diodes clamp the analog input to VDD and AGND. These diodes allow the analog inputs to swing from (AGND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below AGND or above VDD. Note: If the analog input exceeds 50mV beyond the supply rails, limit the current to 2mA.
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13
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
VDD 10 AIN 0.01F CH7 VDD DIN SHDN EXTERNAL CLOCK REFADJ 0.01F SCLK DOUT SSTRB DOUT* 0.1F 10 4.7F SCLK OSCILLOSCOPE
MAX1148 MAX1149
SSTRB VREF 2.2F REF COM CS DGND AGND CH1 CH2 CH3 CH4
MAX1149 VREF = +2.500V MAX1148 VREF = +4.096V
VCOM AIN VREF
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF HEX
Figure 7. Quick-Look Circuit
Table 1. Control Byte Format
BIT 7 (MSB) 6 5 4 3 NAME START SEL2 SEL1 SEL0 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured. 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, connect COM to AGND to perform conversion from 0 to VREF. In bipolar mode, connect COM to VREF/2 to perform conversion from 0 to VREF. See Table 7. Selects clock and power-down modes. PD1 = 0 and PD0 = 0 selects full power-down mode*. PD1 = 0 and PD0 = 1 selects fast power-down mode*. PD1 = 1 and PD0 = 0 selects internal clock mode. PD1 = 1 and PD0 = 1 selects external clock mode. Channel-select bits. The channel-select bits select which of the eight channels are used for the conversion (Tables 2, 3, 4, and 5). DESCRIPTION Start bit. The first logic 1 bit after CS goes low defines the beginning of the control byte.
2
UNI/BIP
1
PD1
0 (LSB)
PD0
*The start bit resets power-down modes.
14
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Table 2. MAX1148/MAX1149 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM -
Table 3. MAX1148/MAX1149 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 + + + + CH0 + CH1 + + + CH2 CH3 CH4 CH5 CH6 CH7
Table 4. MAX1146/MAX1147 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 SEL1 0 0 0 0 SEL0 0 0 1 1 CH0 + + + + CH1 CH2 CH3 COM -
Table 5. MAX1146/MAX1147 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 0 0 1 1 SEL1 0 0 0 0 SEL0 0 1 0 1 + + CH0 + CH1 + CH2 CH3
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1146-MAX1149 in internal clock mode, making the MAX1146-MAX1149 ready to convert with SSTRB high. No conversions should be performed until the power supply is stable. The first logical 1 on DIN with CS low is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros.
Starting a Conversion
Start a conversion by clocking a control byte into DIN. With CS low, a rising edge on SCLK latches a bit from DIN into the MAX1146-MAX1149 internal shift register. After CS falls, the first logic 1 bit defines the control
byte's MSB. Until this start bit arrives, any number of logic 0 bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1146-MAX1149 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers. Set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI transmit a byte and receive a byte at the same time. Using the Typical Application Circuit (Figure 4), the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 14-bit conversion result).
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15
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Digital Output In unipolar input mode, the digital output is straight binary (Figure 14). For bipolar input mode, the digital output is two's complement binary (Figure 15). Data is clocked out on the falling edge of SCLK in MSB-first format. Use internal clock mode if the serial clock frequency is less than 100kHz or if serial clock interruptions could cause the conversion interval to exceed 140s. The conversion must complete in 140s, or droop on the T/H capacitors can degrade conversion results. Internal Clock When configured for internal clock mode, the MAX1146-MAX1149 generate an internal conversion clock. This frees the P from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate up to 2.1MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 8.0s, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the second falling SCLK clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figures 9 and 11). For the most accurate conversion, the MAX1146- MAX1149 digital I/O should remain inactive during the internal clock conversion interval (tCONV). Do not pull CS high during conversion. Pulling CS high aborts the current conversion. To ensure that the next start bit is recognized, clock in 18 zeros at DIN. When internal clock mode is selected, SSTRB does not go into a highimpedance state when CS goes high. A rising edge on SSTRB indicates that the MAX1146-MAX1149 have finished the conversion. The P can then read the conversion results at its convenience.
Clock Modes
The MAX1146-MAX1149 can use either the external serial clock or the internal clock to drive the successive-approximation conversion. The external clock shifts data in and out of the MAX1146-MAX1149. External clock mode allows the fastest throughput rate (116ksps) and serial clock frequencies from 0.1MHz to 2.1MHz. Internal clock mode provides the best noise performance because the digital interface can be idle during conversion. The internal clock mode serial clock frequency can range from 0 to 2.1MHz. Internal clock mode allows the CPU to request a conversion and clock back the results. Bits PD1 and PD0 of the control byte program the clock and power-down modes. The MAX1146-MAX1149 power up in internal clock mode with all circuits activated. Figures 8-11 illustrate the available clocking modes. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the analog-todigital conversion. SSTRB pulses high for two clock periods after the last bit of the control byte. Successiveapproximation bit decisions are made and the results appear at DOUT on each of the next 14 SCLK falling edges (Figures 8 and10). SSTRB and DOUT go into a high-impedance state when CS is high.
CS
SCLK
1 CB1
8
9
16
24
DIN
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
tACQ SSTRB HIGH-Z
tCONV HIGH-Z
DOUT
HIGH-Z
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE
SET TO CB1
OPEN
RESET TO CB1
INPUT T/H
TRACK
HOLD
TRACK
Figure 8. External Clock Mode--24 Clocks/Conversion Timing 16 ______________________________________________________________________________________
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
CS
SCLK
1 CB1
8
9
16
24
DIN
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
tACQ SSTRB
tCONV
DOUT
HIGH-Z
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
INPUT MUX SET ACCORDING TO PREVIOUS CONTROL BYTE
SET TO CB1
OPEN
RESET TO CB1
INPUT T/H
TRACK
HOLD
TRACK
Figure 9. Internal Clock Mode Timing--24 Clocks/Conversion Timing
CS
SCLK
1 CB1
8
1
4
10
11 CB2
18
1
4
10
11
15
DIN
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
START SEL2
SEL1 SEL0 SGL/DIF UNI/BIP
tACQ SSTRB
tCONV
tACQ
HIGH-Z DOUT SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT MUX SET TO CB1 SET TO CB2 D13 D12 D5 D4 D3 D2 D1 D0 D13 D12 D5 D4 D3 D2 D1 D0
INPUT T/H
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 10. External Clock Mode-- Clocks/Conversion Timing 18
Applications Information
Idle Mode
The device is considered idle when all the bits have been clocked out or 18 zeros have been clocked in on DIN.
1) The first high bit clocked into DIN with CS low any time the converter is idle. or 2) The first high bit clocked into DIN after bit 5 of a conversion in progress is clocked onto DOUT (Figures 10 and 11). Toggling CS before the current conversion is complete aborts the conversion and clears the output register. The fastest the MAX1146-MAX1149 can run with CS held low between conversions is 18 clocks per conversion. Figures 10 and 11 show the serial-interface timing necessary to perform a conversion every 18 SCLK cycles.
Start Bit
The falling edge of CS alone does not start a conversion. The first logic high clocked into DIN with CS low is interpreted as a start bit and defines the first bit of the control byte. The device begins to track on the fifth falling edge of SCLK after a start bit has been recognized. A conversion starts on the eighth falling edge of SCLK as the last bit of the control byte is being clocked in. The start bit is defined as follows:
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
CS
SCLK
1 CB1
8
1
4
10
11 CB2
18
1
4
10
11
DIN
START SEL2 SEL1 SEL0 SGL/DIFUNI/BIP PD1
PD0
START SEL2 SEL1 SEL0 SGL/DIF UNI/BIP PD1
PD0
START SEL2
tACQ SSTRB HIGH-Z DOUT SET ACCORDING TO PREVIOUS CONTROL BYTE INPUT MUX SET TO CB1
tCONV
tACQ
tCONV
D13 D12
D5
D4
D3
D2
D1
D0
D13
D12
D5
D4
OPEN
RESET TO CB1
SET TO CB2
OPEN
RESET TO CB2
INPUT T/H
TRACK
HOLD
TRACK
HOLD
TRACK
Figure 11. Internal Clock Mode-- Clocks/Conversion Timing 18
Shutdown and Power-Down Modes
The MAX1146-MAX1149 provide a hardware shutdown and two software power-down modes. Pulling SHDN low places the converter in hardware shutdown. The conversion is immediately terminated and the supply current is reduced to 300nA. Allow 2ms for the device to power-up when the internal reference buffer is used with C REFADJ = 0.01F and C REF = 2.2F. Larger capacitors on C REFADJ and C REF increase the power-up time (Table 6). No wake-up time is needed for the device to power-up from fast powerdown when using an external reference. Select a software power-down mode through the PD1 and PD0 bits of the control byte (Table 1). When the conversion in progress is complete, software powerdown is initiated. The serial interface remains active and the last conversion result can be clocked out. In full power-down mode, only the serial interface remains operational and the supply current is reduced to 300nA. In fast power-down mode, only the bandgap reference and the serial interface remain operational, and the supply current is reduced to 600A.
The MAX1146-MAX1149 automatically wake up from software power-down when they receive the control byte's start bit (Table 1). Allow 2ms for the device to power-up when the internal reference buffer is used with C REFADJ = 0.01F and C REF = 2.2F. Larger capacitors on CREFADJ and CREF increase the powerup time (Table 6). No wake-up time is needed for the device to power-up from fast power-down when using an external reference.
Reference Voltage
The MAX1146-MAX1149 can be used with an internal or external reference voltage. The reference voltage determines the ADC input range. The reference determines the full-scale output value (Table 7). Internal Reference The MAX1146-MAX1149 contain an internal 1.250V bandgap reference. This bandgap reference is connected to REFADJ through a 20k resistor. Bypass REFADJ with a 0.01F capacitor to AGND. The MAX1146/ MAX1148 reference buffer has a 3.277V/V gain to provide +4.096V at REF. The MAX1147/MAX1149 reference buffer has a 2.000V/V gain to provide +2.500V at REF. Bypass REF with a minimum 2.2F capacitor to AGND when using the internal reference. External Reference An external reference can be applied to the MAX1146-MAX1149 in two ways: 1) Disable the internal reference buffer by connecting REFADJ to VDD and apply the external reference to REF (Figure 12). 2) Utilize the internal reference buffer by applying an external reference to REFADJ (Figure 13).
Table 6. Internal Reference Buffer PowerUp Times vs. Bypass Capacitors
CREFADJ* 0.01F 0.1F CREF 4.7F 10F POWER-UP TIMES FROM AN EXTENDED POWER-DOWN 2ms 25ms
*Power-up times are dominated by CREFADJ. 18
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
+5V IN 24k SAR ADC REF REF 3.000V 0.1F 100k GND REFADJ VDD 0.1F DGND AGND +5V 0.047F OUT +3.3V
MAX6163
510k
MAX1146- MAX1149
REFADJ
MAX1146- MAX1149
REFERENCE BUFFER DISABLED
20k 1.250V BANDGAP REFERENCE
Figure 13. Reference Adjust Circuit
with a 0.01F capacitor and bypass REF with a 2.2F capacitor to AGND.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. Output data coding for the MAX1146-MAX1149 is binary in unipolar mode and two's complement binary in bipolar mode with 1 LSB = (VREF/2N), where N is the number of bits (14). Code transitions occur halfway between successive-integer LSB values. Figure 14 and Figure 15 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively.
Figure 12. External Reference Applied to REF
Method 1 allows the direct application of an external reference from 1.5V to VDD + 50mV. The REF input impedance is typically 10k. During conversion, an external reference at REF must deliver up to 210A and have an output impedance less than 10. Bypass REF with a 0.1F capacitor to AGND to improve its output impedance. Method 2 utilizes the internal reference buffer to reduce the external reference load. The REFADJ input impedance is typically 20k. During a conversion, an external reference at REFADJ must deliver at least 100A and have an output impedance less than 100. The MAX1146/MAX1148 reference buffer has a 3.277V/V gain and the MAX1147/MAX1149 has a gain of 2.000V/V. The external reference voltage at REFADJ multiplied by the reference buffer gain is the SAR ADC reference voltage. This reference appears at REF and must be from 1.5V to VDD + 50mV. Bypass REFADJ
Serial Interfaces
The MAX1146-MAX1149 feature a serial interface that is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the CPU's serial interface as a master, so that the CPU generates the serial clock for the ADCs. Select a clock frequency up to 2.1MHz. SPI and MICROWIRE Interface When using an SPI (Figure 16a) or MICROWIRE interface (Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 14-bit result from the ADC. DOUT data transitions on the serial clock's falling
BIPOLAR MODE NEGATIVE FULL SCALE
-V
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE INPUT AND OUTPUT MODES ZERO SCALE FULL SCALE ZERO SCALE POSITIVE FULL SCALE
+ VREF 2 + VCOM
Single-Ended Mode
VCOM
VREF + VCOM
REF + V COM
2
VCOM
Differential Mode
VIN-
VREF + VIN-
-V
REF + V - IN
2
VIN-
+ VREF + VIN - 2
Note: The common mode range for the analog inputs is from AGND to VDD. ______________________________________________________________________________________ 19
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
1 LSB = VREF TWO'S COMPLEMENT BINARY OUTPUT CODE (LSB) 1...111 1...110 1...101 1...100 BINARY OUTPUT CODE (LSB) VREF 16384 VREF 1...111 1...110 1...101 1...100 1 LSB = VREF 16384
0...001 0...000 0...111
VREF
0...011 0...010 0...001 0...000 0 1 2 3 INPUT VOLTAGE (LSB) 16381 16383
0...011 0...010 0...001 0...000 0 1 2 3 8191 8193 8192 INPUT VOLTAGE (LSB) 16381 16383
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function
edge and is clocked into the P on SCLK's rising edge. The first 8-bit data stream contains the first 8-bits of DOUT starting with the MSB. The second 8-bit data stream contains the remaining 6 result bits. QSPI Interface Using the high-speed QSPI interface (Figure 17) with CPOL = 0 and CPHA = 0, the MAX1146-MAX1149 support a maximum fSCLK of 2.1MHz. One 16-bit reading is necessary to obtain the entire 14-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the P on SCLK's rising edge. The first 14 bits are the data. PIC16/PIC17 SSP Module Interface The MAX1146-MAX1149 are compatible with a PIC16/PIC17 microcontroller (C), using the synchronous serial-port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure 18 and configure the PIC16/PIC17 as system master. Initialize the synchronous serial-port control register (SSPCON) and synchronous serial-port status register (SSPSTAT) to the bit patterns shown in Tables 8 and 9. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings are necessary to obtain the entire 14-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the remaining bits, D5 through D0.
I/O SCK MISO VDD
CS SCLK DOUT
I/O SK SI
CS SCLK DOUT
SPI
MICROWIRE
SS
MAX1146- MAX1149
MAX1146- MAX1149
Figure 16a. SPI Connections 20
Figure 16b. MICROWIRE Connections
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VREF
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
VDD
CS SCK MISO CS SCLK VDD DOUT
VDD
SCLK DOUT
CS
SCK SDI I/O
QSPI
SS
MAX1146- MAX1149
PIC16/PIC17
MAX1146- MAX1149
GND GND
Figure 17. QSPI Connections
Figure 18. SPI Interface Connection for a PIC16/PIC17 Controller
Table 8. Detailed SSPCON Register Content
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PICI6/PICI7 SETTINGS X X 1 0 0 0 0 1 Synchronous serial port mode select bit. Sets SPI master mode and selects FCLK = fOSC / 16. SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write collision detection bit. Receive overflow detect bit. Synchronous serial port enable bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial-port pins. Clock polarity select bit. CKP = 0 for SPI master mode selection.
Table 9. Detailed SSPSTAT Register Content
CONTROL BIT SMP CKE D/A P S R/W UA BF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAX1146-MAX1149 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SPI data input sample phase. Input data is sampled at the middle of the data output time. SPI clock edge select bit. Data is transmitted on the rising edge of the serial clock. Data address bit. Stop bit. Start bit. Read/write bit information. Update address. Buffer full status bit.
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Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
TMS32OLC3x Interface Figure 19 shows an application circuit to interface the MAX1146-MAX1149 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 20. Use the following steps to initiate a conversion in the MAX1146-MAX1149 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are connected together with the MAX1146-MAX1149 SCLK input. 2) Drive the CS of the MAX1146-MAX1149 low through the XF_ I/O port of the TMS320 to clock data into the MAX1146-MAX1149 DIN. 3) Write an 8-bit word (1XXXXX11) to the MAX1146-MAX1149 to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX1146-MAX1149 SSTRB output is monitored by the FSR input of the TMS320. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1146-MAX1149. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 14-bit conversion result followed by 2 trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1146-MAX1149 until the next conversion is initiated.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system performance. Boards should have separate analog and digital ground planes. Ensure that digital and analog signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. Figure 4 shows the recommended system ground connections. Establish an analog ground point at AGND and a digital ground point at DGND. Connect all analog grounds to the star analog ground. Connect the digital grounds to the star digital ground. Connect the digital ground point to the analog ground point directly at the device. For lowest noise operation, the ground return to the star ground's power supply should be low impedance and as short as possible.
XF TMS320LC3x CLKX CLKR DX DR FSR
CS
SCLK
MAX1146- MAX1149
DIN DOUT SSTRB
Figure 19. MAX1146-MAX1149-to-TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
SGL/DIF
UNI/BIP
PD1
PD0
SSTRB
HIGH-Z
DOUT
MSB
B12
B1
LSB
HIGH-Z
Figure 20. TMS320 Serial-Interface Timing Diagram 22 ______________________________________________________________________________________
Multichannel, True-Differential, Serial, 14-Bit ADCs
High-frequency noise in the VDD power supply degrades the device's high-speed performance. Bypass the supply to the digital ground with 0.1F and 4.7F capacitors. Minimize capacitor lead lengths for best supply-noise rejection. Connect a 10 resistor in series with the 0.1F capacitor to form a lowpass filter when the power supply is noisy.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
MAX1146-MAX1149
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1146-MAX1149 are measured using the end-point method.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: V 2 + V32 + V4 2 + V52 THD = 20 x log 2 V1
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Chip Information
TRANSISTOR COUNT: 5589 PROCESS: BiCMOS
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23
Multichannel, True-Differential, Serial, 14-Bit ADCs MAX1146-MAX1149
Pin Configurations
TOP VIEW
CH0 1 CH1 2 CH2 3 CH3 4 N.C. 5 N.C. 6 N.C. 7 N.C. 8 COM 9 SHDN 10 20 VDD 19 SCLK 18 CS 17 DIN CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 SHDN 10 20 VDD 19 SCLK 18 CS 17 DIN
MAX1146 MAX1147
16 SSTRB 15 DOUT 14 DGND 13 AGND 12 REFADJ 11 REF
MAX1148 MAX1149
16 SSTRB 15 DOUT 14 DGND 13 AGND 12 REFADJ 11 REF
TSSOP
TSSOP
24
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Multichannel, True-Differential, Serial, 14-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1146-MAX1149
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
TSSOP4.40mm.EPS

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